1. Field of the Invention
The present invention relates to a semiconductor device having a multilayer interconnection structure and a method of manufacturing thereof, and more particularly, to improvement of an interconnection contact structure in a step-graded region and a manufacturing method thereof.
2. Description of the Background Art
In the field of semiconductor devices, increase of integration density and miniaturization of an element structure are required. In order to meet such requirements, a structure is conceived in which a plurality of elements are stacked three-dimensionally on a surface of a semiconductor substrate. Although such a stacked type semiconductor device increases the integration density of a main surface of the semiconductor substrate, several problems arise from the fact that an interconnection layer is disposed on a region having an abrupt change in level.
A structure of an SRAM (Static Random Access Memory) will be described as an example of a semiconductor device having a structure in which semiconductor elements are stacked on a substrate. FIGS. 17 through 19 show a structure of a memory cell of a CMOS (Complementary Metal Oxide Semiconductor) type SRAM using a thin film transistor as a load, which is disclosed in "A Memory Cell with Polysilicon Thin Film Transistor (TFT) for a 4 Mbit SRAM", Tsutsumi et al., Institute of Electronics and Communication Engineers of Japan Technical Report, Vol. 90, No. 48, pp.7-13. FIG. 20 is an equivalent circuit diagram of a memory cell of this SRAM. Referring to FIG. 20, a memory cell of a CMOS type SRAM has a pair of CMOS inverters. One CMOS inverter includes an n channel MOS drive transistor 20a and a p channel MOS thin film load transistor 21a. The other CMOS inverter includes an n channel MOS drive transistor 20b and a p channel MOS thin film load transistor 21b. The gates of transistors 20a, 21a of said one CMOS inverter are cross-coupled to a storage node 25b common to transistors 20b, 21b of the other CMOS inverter. The gates of transistors 20b, 21b of the other CMOS inverter are cross-coupled to a storage node 25a common to transistors 20a, 21a of the one CMOS inverter to form a flip-flop circuit. The sources of p channel MOS thin film load transistors 21a, 21b are connected to a power supply 23. Each of the sources of n channel MOS drive transistors 20a, 20b is connected to ground. Storage nodes 25a, 25b of the flipflop circuit are connected to n channel MOS transfer transistors 22a, 22b, respectively. The gates of n channel MOS transfer transistors 22a, 22b are connected to a word line 27. The drain regions of n channel MOS transfer transistors 22a, 22b are connected to bit lines 26a, 26b, respectively.
An operation of writing information into a memory cell will be described. For example, if storage node 25a and storage node 25b are set at a ground potential and a power supply potential, respectively, then bit line 26a and bit line 26b are set at ground level and power supply level, respectively. n channel MOS transfer transistors 22a, 22b are turned on by applying a predetermined potential to word line 27.
An operation of reading information from a memory cell will be described. Bit lines 26a, 26b are connected to a sense amplifier circuit. Under this state, word line 27 is supplied with a predetermined potential to turn on n channel MOS transfer transistors 22a, 22b. As a result, the potentials of storage nodes 25a, 25b are read out to bit lines 26a, 26b.
A specific structure of a memory cell of an SRAM will be described hereinafter with reference to FIGS. 17 through 19. For the sake of simplifying the description, the memory cell is divided into a lower layer portion (FIG. 17) and an upper layer portion (FIG. 18) with respect to a substrate. FIG. 19 is a sectional structural view taken along line X--X in FIGS. 17 and 18.
Referring to FIGS. 17 through 19, a memory cell of an SRAM includes n channel MOS drive transistors 20a, 20b and n channel MOS transfer transistors 22a, 22b in a lower layer region near the surface of a silicon substrate 1. In an upper layer region formed on the main surface of silicon substrate 1 with an interlayer insulating layer 9 thereunder, p channel MOS thin film load transistors 21a, 21b are arranged.
Referring mainly to FIG. 19, a p well region 2 is formed at the surface of silicon substrate 1. A field oxide film 4 and a p.sup.+ isolation region 3 are formed in an element isolation region on the main surface of p well region 2. An n channel MOS drive transistor 20a and an n channel MOS transfer transistor 22b each include n.sup.+ source/drain regions 7, a gate film 5 and a gate electrode 6. Gate electrode 6 has a polycide structure including a polycrystalline silicon layer 6a and a metal silicide film 6b formed on polycrystalline silicon layer 6a.
The surface of silicon substrate 1 is covered with a thick interlayer insulating layer 9. The p channel thin film load transistor 21b is formed on the surface of interlayer insulating layer 9. A thin film transistor 14 (identical to p channel thin film load transistor 21b) includes a gate electrode 8b formed on the surface of interlayer insulating layer 9, a gate oxide film 13 covering the surface of gate electrode 8b, p.sup.+ source/drain regions 12a, 12c, and a channel region 12b. p.sup.+ source/drain regions 12a, 12c and channel region 12b are formed in a thin polycrystalline silicon layer having a thickness of about 20 nm. Gate electrode 8b includes p type impurities.
An interconnection structure of storage node 25b will be described hereinafter to which the gate electrode of n channel MOS drive transistor 20a formed in the lower layer, the n.sup.+ source/drain regions of n channel MOS transfer transistor 22b and the p.sup.+ source/drain regions of p channel MOS thin film load transistor 21b formed in the upper layer are connected. An opening 16 is formed in interlayer insulating layer 9. Inside opening 16, gate electrode 6 of n channel MOS drive transistor 20a and one of n.sup.+ source/drain regions 7 of n channel MOS transfer transistor 22b are exposed. An interconnection layer 8a of polycrystalline silicon is formed inside opening 16 to be connected to both gate electrode 6 of n channel MOS drive transistor 20a and n.sup.+ source/drain region 7 of n channel MOS transfer transistor 22b. Such a contact structure is referred to as a "shared contact". A portion of interconnection layer 8a extends onto the surface of interlayer insulating layer 9. This is the gate electrode of p channel MOS thin film load transistor 21a. A polycrystalline silicon layer constituting a p.sup.+ source/drain region 12a of p channel MOS thin film load transistor 21b is connected to the surface of the interconnection layer 8a. Interconnection layer 8a is formed of polycrystalline silicon, and includes p type impurities to provide conductivity. At the bottom of opening 16, a titanium silicide layer 11 is formed between interconnection layer 8a and source/drain region 7. Titanium silicide layer 11 prevents the formation of a pn junction caused by direct contact between interconnection layer 8a of p type and source/drain region 7 of n type. Such a structure is referred to as a "direct contact" in which interconnection layer 8a disposed on the surface of interlayer insulating layer 9 is connected to a lower layer, for example, an impurity region formed on the silicon substrate, through opening 16.
However, there is a problem that an interconnection layer cannot be easily patterned when a direct contact structure having great differences in level is formed such as the interconnection layer 8a in the above-mentioned memory cell of an SRAM. FIG. 21 is a sectional view showing a manufacturing step of forming interconnection layer 8a shown in FIG. 18. Following the formation of opening 16 in interlayer insulating layer 9, polycrystalline silicon layer 8 is deposited all over the surface by, for example, a CVD (Chemical Vapor Deposition) method. Then, a resist is applied onto the surface of polycrystalline silicon layer 8. The resist is exposed to a prescribed pattern by photolithography, and then developed to form a resist mask. Next, polycrystalline silicon layer 8 is etched using the resist mask to form interconnection layer 8a and gate electrode 8b of thin film transistor 14 (p channel thin film load transistor 21b).
It can be seen from FIG. 21 that polycrystalline silicon layer 8 is formed on the surface of interlayer insulating layer 9 having an abrupt change in level. The step-graded portion of the polycrystalline silicon layer is significant in the vicinity of opening 16. It is extremely difficult to form a very small resist mask on the surface of polycrystalline silicon layer 8 having such an abrupt change in level through the current exposure technology.
Recently, the step-graded portion is so abrupt that the range of the depth of a focus of an exposure device is often exceeded in a semiconductor integrated circuit. Therefore, resolution of a resist pattern was decreased, giving rise to a problem that a desired design resist pattern configuration could not be obtained in interconnection layer 8a of polycrystalline silicon. Degradation in the interconnection pattern accuracy will prevent reduction in size of the interconnection to reduce reliability thereof.